Not Applicable.
The present embodiments relate to electronic circuits and are more particularly directed to a metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) transistor having a configuration for enhanced electrostatic discharge (xe2x80x9cESDxe2x80x9d) protection.
Many contemporary integrated circuits include two sets of transistors, where a first transistor set operates at a first operating voltage while a second transistor set operates at a second and different operating voltage. For example, in various modem circuits a first voltage is used for transistors implemented at the input/output (xe2x80x9cI/Oxe2x80x9d) level while a second and lower voltage is used for transistors implemented in the operational core of the circuit. In these cases, transistors suitable for use at the higher I/O voltages are required and, thus, the design of such transistors must take this factor into account.
In addition to having a higher operating voltage, typically the I/O transistors are more susceptible to ESD as opposed to the core transistors because the former generally isolate the latter from external power effects. ESD occurs due to a relatively short period of relatively high voltage or current imposed on a device. For example, ESD can be caused by the human body, by poorly grounded machinery such as test equipment, or in electrically noisy environments as may be incurred in automotive applications or in consumer applications, including computers. Moreover, various testing has been developed to ensure that certain circuits comply with ESD standards, such as a test circuit mandated by MIL-STD 883B. In any event, due to the risk of ESD, devices are often engineered and tested to ensure that they can withstand certain levels of ESD.
By way of further background to the type of transistors used both in I/O and core locations of prior art circuits, FIG. 1a illustrates a cross-sectional view of a prior art MOS transistor 10 which, by way of example, is an n-channel (NMOS) transistor. Transistor 10 is formed using a substrate 20 which, in the example of FIG. 1a, is formed from a p-type semiconductor material and is therefore labeled with a xe2x80x9cPxe2x80x9d designation. Two shallow trench isolation (xe2x80x9cSTIxe2x80x9d) regions 221 and 222 are formed in substrate 20 and may be various insulating materials such as silicon oxide or silicon nitride. A gate dielectric 24 is formed over substrate 20, and it may be an oxide, a thermally grown silicon dioxide, a nitride, an oxynitride, or a combination of these or other insulators. A gate conductor 26 is formed over gate dielectric 24, such as by forming a layer of material which is patterned and etched to form gate conductor 26. Further, gate conductor 26 is typically formed from polysilicon, although other materials may be used. For the sake of reference, gate conductor 26 is also shown by a schematic indication in FIG. 1a with the identifier xe2x80x9cG1.xe2x80x9d Two lightly doped diffused regions 281 and 282 are formed within substrate 20 and are self-aligned with respect to the sidewalls of gate conductor 26 and also extend slightly under gate conductor 26. In the present example, lightly doped diffused regions 281 and 282 are n-type regions. Thereafter, sidewall insulators 301 and 302 are formed along the sidewalls of gate conductor 26. Next, doped regions 321 and 322 are formed within substrate 20 and are self-aligned with respect to sidewall insulators 301 and 302, respectively. Doped regions 321 and 322 are formed using the same type of conductivity implant as lightly doped diffused regions 281 and 282, but typically with a greater concentration of those dopants and/or using a greater implant energy as compared to that used to form lightly doped diffused regions 281 and 282. Each of doped regions 321 and 322 combines with a corresponding one of lightly doped diffused regions 281 and 282 to form what are generally structurally identical and symmetric regions relative to gate conductor 26; thus, these regions are sometimes referred to as source/drain regions. However, for the sake of reference, in FIG. 1a the combination of region 281 and region 321 is considered to provide the source of transistor 10 and is schematically labeled xe2x80x9cS1xe2x80x9d, and the combination of region 282 and region 322 is considered to provide the drain of transistor 10 and is schematically labeled xe2x80x9cD1.xe2x80x9d
The operation of transistor 10 is well known in the art and, thus, the following discussion only addresses aspects relating to observations by the present inventors and as improved upon by the preferred embodiments discussed later. Under normal operation, when a proper gate-to-source potential is applied to transistor 10, then current conducts between source S1 and drain D1. As appreciated from FIG. 1a, this current path is between the inward boundaries of lightly doped diffused regions 281 and 282 and below gate dielectric 24, and this area is known as the transistor channel.
To further illustrate the operation of transistor 10 and particularly to illustrate an aspect during an ESD event, FIG. 1b illustrates a plan view of various components of transistor 10. Generally, FIG. 1b illustrates the source S1, gate G1, and drain D1 of transistor 10. Further, the channel spans between two dashed lines, where those lines are intended to illustrate the inward boundaries of lightly doped diffused regions 281 and 282 as they exist below gate G1. Given the location of the channel, current under normal operation travels uniformly in the horizontal dimension relative to FIG. 1b (and FIG. 1a). However, under ESD events, it has been observed that there may be an area of so-called runaway current, that is, a particular physical location within the channel where a considerably greater amount of current passes as opposed to other locations within the channel. Such a physical location is referred to as a xe2x80x9cfilamentxe2x80x9d and, for sake of illustration, one such filament is shown by way of a bi-directional arrow designated F1 in FIG. 1b. Moreover, an ESD event may cause damage to transistor 10 because most of the energy passes by way of filament F1, thereby posing the greatest potential for device damage along the path of that filament.
In view of the above, there arises a need to improve upon the prior art as is achieved by the preferred embodiments described below.
In the preferred embodiment, there is a method of forming a transistor in a semiconductor active area. The method forms a gate structure in a fixed relationship to the semiconductor active area thereby defining a first source/drain region adjacent a first structure sidewall and a second source/drain region adjacent a second gate sidewall. The method also forms a lightly doped diffused region formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure. Other aspects are also disclosed and claimed.